1. Field of the Invention
The present invention relates to a protection structure against electrostatic discharges (ESD) for an electronic device integrated on a SOI substrate.
Specifically, the invention relates to a protection structure against electrostatic discharges (ESD) for a semiconductor electronic device that is integrated inside a well, the well being formed on a SOI substrate and isolated dielectrically by a buried oxide layer and an isolation structure including at least a dielectric trench filled with a filler material.
The invention further relates to an integration process of a protection structure against electrostatic discharges (ESD) for an electronic device integrated in a SOI substrate.
The invention relates, particularly but not exclusively, to protective structures for devices that are produced with BiCMOS technologies inside wells, which wells are isolated dielectrically and formed on a SOI substrate, and the description that follows makes reference to this field of application for convenience of illustration only.
2. Description of the Related Art
It is well known that semiconductor-integrated electronic devices require to be protected against electrostatic discharge (ESD) phenomena.
An ESD protection structure for an integrated electronic device usually comprises an active protection device (a diode or a transistor), which in the event of a high charge being injected incidentally into the chip from the ambient will protect the chip against the high energy level that is created during the transient associated with the electrostatic discharge.
In particular, the integrated electronic device, also referred to as the primary device, is protected from ESD by the provision of an alternative path to ground for the flow of energy that associates with the electrostatic discharge.
From a manufacturer's standpoint, achieving electrostatic discharge protection structures is to provide low-resistivity and low-capacitance devices to be integrated, the devices occupying but a small proportion of the integration area compared to the primary device to be protected.
With standard technologies, where the integration well isolation is of the junction type, ESD protection structures are usually in the form of vertically operating components effective to afford, in particular, an electric path to ground having low resistivity and low capacitance. With such technologies, integrating electrostatic discharge protection structures is fairly simple, because a path to ground is inherently available through the substrate where the devices are integrated.
On the other hand, with SOI substrate integration technologies, no natural path to ground is available because the substrate is isolated dielectrically from the integration well by a buried oxide (BOX) layer. Accordingly, these technologies provide for no vertical diodes or transistors obvious to use as ESD protection structures.
In particular, devices realized on SOI substrates are characterized by the buried oxide layer (BOX) providing vertical isolation, and include a lateral type of isolation structure, in particular a dielectric trench structure, which can only provide lateral isolation.
Thus, the continuity from the buried oxide layer to the dielectric trench lateral isolation structure provides full dielectric isolation for the devices that are realized within suitable integration or isolation wells. The isolation wells are bordered by the buried oxide layer (BOX) and the dielectric trench lateral isolation structure.
Shown schematically in FIG. 1 is a portion 1 of a semiconductor device, which includes essentially a dielectrically isolated well 2 formed conventionally with a technology that employs a SOI substrate.
In particular, the semiconductor device portion 1 includes a substrate or wafer handle region 3 which is customarily to provide mechanical support. When complex devices are integrated, it is sometimes utilized also as an active silicon layer.
Formed on the substrate region 3 is a buried oxide (BOX) layer 4, which is used as a vertical isolation element for the well 2, lateral isolation for the well being provided by a lateral oxidation region 5 coated with a nitride layer 6. The region 5 is formed around the edges of the well 2 in dielectric contact with the buried oxide layer 4.
In particular, the combination of two lateral oxidation regions 5 plus the respective nitride layers 6, and the underlying portion of the buried oxide layer 4, forms a so-called dielectric trench type of isolation structure 7. The dielectric trench isolation structure 7 is usually filled with filler material 8, most often polysilicon.
Thus, an integration region 9 is defined within the well 2 for various components (device wafer) that are isolated dielectrically from the remainder of the semiconductor device. For example, a primary device 10 requiring protection may be integrated in the integration region 9.
Protection structures integrated with standard technologies cannot be used with a SOI technology device 10. In particular, the absence of conductive structures of the vertical type disallows dissipation of the energy that associates with the discharge through the substrate, and enforces use of protection structures of the lateral type.
However, lateral protection structures are bound to have an extended peripheral dimension and, consequently, to occupy a large proportion of the integration area available on the chip.
This because the amount of ESD energy involved can be considerable, and powerful protection structures are needed whose size cannot be insignificant relative to the primary device to be protected.
Additionally to lacking natural structures of the vertical type directly connected to the substrate, devices integrated with SOI technologies have disadvantages due to a high thermal impedance toward the substrate and the presence of SOI layers that may be very thin.
In particular, the high thermal impedance toward the substrate interdicts prompt dissipation of the energy associated with ESD occurrences. This leads to increased surface temperature and eventual failure of the primary device to be protected, due to secondary breakdown phenomena.
Also, a very thin SOI layer results in high current densities being created in the silicon regions where the active devices are realized, and causes localized breakdowns due to the high power density that must be dissipated through small silicon volumes.
Thus, it has been known to use, where SOI technologies are involved, protection structures of the lateral type or structures that, although of the vertical type locally, are in any case contacted by the surface. Such a protection structure 11 of the lateral type is integrated inside the well 2, specifically in the integration region 9, as shown schematically in FIG. 2.
A known lateral protection structure 11 is discussed, for example, in an article by K. Verhaege et al., “Analysis of Snapback in SOI NMOSFETs and its Use for an SOI ESD Protection Circuit,” Proceedings of the IEEE SOI Conference, 1992, pages 140-141. According to the article, a MOS transistor realized with SOI technology is used as an ESD protection device.
A similar approach is described in U.S. Pat. No. 4,989,057 to Lu, wherein an ESD protection structure comprises essentially a MOS transistor.
Likewise, Voldman et al. in an article, “CMOS-on-SOI ESD Protection Networks,” EOS/ESD Proceedings, September 1996, discuss using diode-configured MOS devices as ESD protection devices in the presence of thin SOI layers.
SOI substrate integrated devices provided with ESD protection structures are in all cases less robust than devices integrated in standard substrates by at least a factor of two, as shown by Chan et al. in an article “Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers,” IRPS, 1994.
In the instance of SOI substrates, moreover, conventional protection structures have a lateral silicon occupation with respect to the device to be protected. Lastly, the structures proposed heretofore are all of the MOS type.
From a manufacturer's point of view, these two factors respectively bring about an unacceptable increase in the size of the chip that has to comprise the primary device with its protection structure, and significantly increased overall capacitance through the device due to the polysilicon gate structures that are inherent to unipolar components.
Also known is to use bulk transistors for ESD protection, as described in U.S. Pat. No. 4,889,829 to Kawai and U.S. Pat. No. 5,399,507 to Sun.
In particular, Kawai describes a process for producing protection bulk transistors in the substrate and SOI transistors in the isolation layer, respectively, wherein the protection bulk transistors are integrated adjacent to the active area of the device to be protected, in the same plane and using dedicated maskings.
This requires added integration area to the primary device, and brings about problems of planarity due to the complicated layout that a protection structure comprising bulk transistors involves inherently.
Sun teaches providing a thin SOI combination layer, with the ESD protection structures being integrated in the bulk layer. In particular, implanted and masked oxygen is used in making these structures. Once again, the ESD protection structures are of the MOS type and integrated adjacent to the device to be protected.
Sun's protection structure removes the critical want of planarity that affects Kawai's disclosure, but introduces dislocations within the silicon as a consequence of the oxygen implantation, so that the active device to be protected is to be integrated sufficiently far from the protection structure to prevent such dislocations from occasioning faultiness.
Again, more silicon area must be made available, which is commercially unacceptable.
Other prior solutions have been directed either to provide fully bulk-type protection structures or to use the silicon region under the isolation layer as an active area where to integrate the ESD protection structures, as disclosed in U.S. Pat. No. 6,071,803 to Rutten. The last-mentioned reference teaches a method of producing an ESD protection structure for circuitry that is integrated in substrates of the SOI type, whereby trenches filled with a conductive material place the devices integrated in the SOI layer overlying the isolation layer (device wafer) in contact with the substrate (handle wafer).
In this way, an ESD protection structure can be formed with a preferential electric path to ground because it would be integrated in the substrate, and can be a bulk structure of an adequately large size to withstand energy discharge. Also, such a protection structure occupies but a trivial amount of lateral silicon area in the SOI layer compared to the primary device, namely an area not larger than the area of the trench.
Although advantageous on several counts, this prior solution still has a number of drawbacks. In particular, the connection between the active devices integrated in the SOI layer and the protection structure in the substrate, through the conductive trench, can weaken the dielectric isolation of the well where the primary device is fabricated. Leakage toward the substrate is likely to occur, and parasitic capacitances and components to appear during dynamic operation of the primary device to be protected, such that the whole device can no longer be considered dielectrically isolated.
Furthermore, in order to avoid high current density values within the conductive trench, more trenches become necessary to improve the protection structure, making the dielectric isolation of the device even weaker.
In addition, the steps of piercing the isolating layer through the trench and filling with conductive material are additive to the manufacturing process, and are cost-intensive for the manufacturer.
To summarize, no prior art solutions provide ESD protection structures for technologies on SOI substrates, which can perform satisfactorily from all points of view and be commercially advantageous, since the lateral integration of such structures would either lead to expanded silicon occupation or incomplete dielectric isolation of the device to be protected. Thus, these prior protection structures detract from the advantages that are inherent to technologies of the SOI type.